STX Cadware Incorporated

Test-chips are always at the leading edge of process technology and advanced circuit development. Used by both "fabless" manufacturers and those with large investments in semi-conductor fabrication, these tasks are, in many cases, still performed manually and represent excessive costs and bottlenecks in a critical technology area.STX TLAF™ lets you input process rules, select components, input individual module specifications, and generate layouts in a matter of minutes. STX TLAF™ automates this process for faster, cheaper, and better test die creation.

Structured for Success

The STX Test-Chip Layout Autogenerator Framework provides your designers the underlying programmatic structure that facilitates rapid development and layout of test chips. Whether you are improving physical device manufacturing processes or experimenting with sets of controlled systematic variations in layout for better device modeling and characterization, STX TLAF™ consistently delivers test-chip layouts on time, within your budget, and in your Cadence tool environment.

• Fully Cadence compatible.
• No need for third party tools or data conversions.
• Standard library of test components eliminates or reduces development cost for new generators.
• Leverages your existing Pcells or in-house custom device generators.
• Generators are fully maintained and upgraded as needed, reducing support costs.

Generator Library